The microprocessor architecture design has entered the era of thread level parallelism 目前微处理器系统结构设计已经进入线程级并行的时代。
The appearance of tlp greatly improves the performance and throughput of the processors 线程级并行性的开发大大提高了处理器的性能和处理能力。
Based on the dlx simulator , smarcof is modified with sma specific extension and heuristic optimizing rules . simulation of spec code shows that above rules could exploit hybrid parallelism effectively with rather low overhead 基于spec代码的模拟表明该方式能够有效的挖掘系统的潜力,实现深度的指令级并行和线程级并行开发。
With such research background , this dissertation focuses on the research of hardware techniques for thread level parallelism in high performance microprocessors , especially the multithreaded microprocessor which has superscalar execution core 在这种背景下,本文研究支持线程级并行的硬件技术,尤其是执行单元为超标量结构的多线程处理器。