memory bandwidth造句

• Memory bandwidth is very small
  要求内存带宽较小。
• This is the fastest way of animating , but its memory bandwidth is too high
  它确实是一个完成动画的快速方法，但其对内存带宽要求过高。
• 3 thoroughly reviewed memory bandwidth requirement of sma processor and difference of various instruction fetch policies . to improve cache performance under sma model , the paper introduces hardware software co - operative optimization
  3针对多线程模式下访存负荷加重的问题，为sma模型设计了软硬件协同预取机制，并为sma模型设计了cachefilter来消减无效预取。
• And to improve the efficient of the packet switching , researchers suggest people use the parallel packet switches ( pps ) , and pps has been studied as a way to overcome the memory bandwidth limitation and to scale - up switch speeds
  在网络速度要求不断提高的情况下,存储器件速度跟不上需求,许多的研究者提出尝试使用多平面的交换结构提高数据交换的速度,解决高速网络中的交换问题。
• And it has significance in multimedia communication , digital multimedia broadcast and portable consumer electronics etc . the real - time implementation of video coding requires very high computation power and memory bandwidth
  它面向移动多媒体应用,对新一代移动多媒体通信、数字多媒体广播、便携式视听消费电子产品等产业的发展具有重要意义。数字视频数据压缩的实时实现对处理器的计算能力和带宽要求很高。
• This is not only because the increased computing power also allows users to produce more and more complex datasets , but also because memory bandwidth grows at a significantly slower rate than processing power and becomes the major bottleneck when dealing with massive datasets
  这不仅是因为计算能力的增长允许用户来创建更为复杂的数据集，也是因为内存带宽的发展速度明显的低于处理器增长的速度，而这成为处理大规模数据集的主要瓶颈。
• In the part 2 of advanced audio video coding standard avs - p2 , many efficient coding tools are adopted in motion compensation , such as new motion vector prediction , symmetric matching , quarter precision interpolation , etc . however , these new features enormously increase the computational complexity and the memory bandwidth requirement , which make motion compensation a difficult component in the implementation of the avs hdtv decoder
  在avs - p2中传统的运动补偿技术被进一步改进以获得更好的编码性能。这些新的特性包括：预测块大小可变化1616到88基于矢量三角形的新型mv预测多参考帧最多2帧或4场直接或对称模式匹配不限制的mv和1 4精度像素插值等。
• The efficiency of the controller can be 36 . 36 % or 72 . 73 % when data length is 1 or 2 . when the data length is 4 or above , the efficiency can be 100 % . the effect that on - chip cache has on memory bandwidth is analyzed , and an on - chip cache scheme that can reduce 50 % reference data read
  通过多体交错式存取,本文设计的ddrsdram控制器在存取数据长度为1或2个字时,带宽利用率分别为36 . 36 %和72 . 73 % ,存取数据长度为4个字时,带宽利用率可达到100 % ,满足了高清实时解码的要求。