As vlsi design becomes larger and takes up much longer time , verification and debugging of logic design become the dominating part of total design period . in order to reduce the time for obtaining a valid design , many verification techniques have been studied . fpga is relatively useful in such case due to its rapid implementation 随着现代vlsi设计规模迅速扩大、芯片的设计和实现周期变长,验证和调试在asic设计中占有越来越重要的地位,相应的在整个asic设计流程中,验证和调试将占用更多的时间。
We pointed out the features of this infrastructure , analyzed the basis of modern applied software - mvc mode , elaborated the j2ee system infrastructure used by this system , and analyzed the integrated infrastructure system . then from the system ' s real requirement , with the object - oriented method , we used an advanced modeling tool - rose to model the system ' s requirement and logic design , then finally implemented the system design . this system uses powerdesigner to do the data modeling , jbuilder as the development tool , and struts framework to realize the separation of the expressing layer , the logic layer and the data layer 通过研究和开发宽带boss ,了解了有关boss的基本概念、模型、发展现状及发展趋势;然后分析了现代应用软件的架构: b s架构,指出了此种架构的特点,并分析了现代应用软件架构的基础? ? mvc模式,详细介绍了本系统所采用的j2ee体系架构,对组成本系统的整体架构体系进行分析;随后从本系统的实际需求出发,以面向对象的方法,采用先进的建模工具rose对系统的需求及逻辑设计进行建模;最后对系统设计加以实现,本系统用powerdesigner对数据建模,以jbuilder为开发工具,采用struts框架实现表示层、逻辑层及数据层的分离,数据层采用数据持久化技术hibernate ,从而可以隐藏访问数据源的数据访问api ,简化开发。
If there is such a tool , for the control logic designed in stateflow , the system engineer could provide the rtl description of the system to the ic engineer . thus , the work of programming in hdl will be omitted , and the ic engineer could have more time to the design coming - up 如果存在这样的转换工具,对于使用stateflow设计的控制逻辑部分,系统工程师可以直接向ic工程师提供系统的rtl描述,省去了ic工程师在硬件描述语言上的编程工作,使得他能够将更多的精力放在后续的设计中。